Integrated circuit technology has revolutionized various fields including computers, control systems, telecommunications, and imaging. One field in which integrated circuitry is widely used is in video imaging. Different types of semiconductor imagers include: charge coupled devices, photodiode arrays, charge injection devices, and hybrid focal plane arrays. Many of these devices include pixels that are arranged in sensor arrays to convert light signals into electrical signals.
It is desirable in image sensors to remove KTC noise and fixed pattern noise (FPN) from the signals that originate at the pixels and pass through the image sensor circuitry. Fixed pattern noise that is produced in CMOS image sensors is related to the fact that there are typically different readout circuits for each pixel and also different column amplifiers for each column of a CMOS image sensor pixel array. The readout circuits each generate pixel fixed pattern noise and the column amplifiers each generate column fixed pattern noise due to circuit and process variations. KTC noise is produced during the switching of signals by switches.
One prior art circuit for reducing KTC noise and fixed pattern noise is shown in "Progress in CMOS Active Pixel Sensors," by S. K. Mendis et al., Proceedings of the SPIE--The International Society for Optical Engineering, Volume 2172, 1994, pages 19-29. The circuit shown in the Mendis et al. reference is patented in U.S. Pat. No. 5,471,515 to Fossum et al. FIG. 3 of the Fossum et al. patent is reproduced herein as FIG. 1.
FIG. 1 is a simplified schematic diagram of one pixel cell of a focal plane array of many such cells formed in an integrated circuit. Referring to FIG. 1, a photogate consists of a relatively large photogate electrode 30 overlying a substrate 20. A charge transfer section consists of a transfer gate electrode 35 adjacent to the photogate electrode 30, a floating diffusion 40, a reset electrode 45, and a drain diffusion 50. A readout circuit consists of a source follower field effect transistor (FET) 55, a row select FET 60, a load FET 65, and a correlated double sampling circuit 70. A bit line BL couples the top of the load FET 65 to the sampling circuit 70. The bit line BL is the line to which all of the pixels of a column are connected and onto which the pixel signals from each pixel in a column are read.
The readout circuit 70 consists of a signal sample and hold (S/H) circuit including an S/H FET 200 and a signal store capacitor 205 connected through the S/H FET 200 and through the row select FET 60 to the source of the source follower FET 55. The other side of the capacitor 205 is connected to a source bias voltage VSS. The one side of the capacitor 205 is also connected to the gate of an output FET 210. The drain of the output FET 210 is connected through a column select FET 220 to a signal sample output node VOUTS and through a load FET 215 to the drain voltage VDD. The output FET 210, the column select FET 220, and the load FET 215 essentially comprise an output buffer stage of the readout circuit 70. A signal called "signal sample and hold" (SHS) briefly turns on the S/H FET 200 after the charge accumulated beneath the photogate electrode 30 has been transferred to the floating diffusion 40, so that the capacitor 205 stores the source voltage of the source follower FET 55 indicating the amount of charge previously accumulated beneath the photogate electrode 30.
The readout circuit 70 also consists of a reset sample and hold (S/H) circuit including an S/H FET 225 and a signal store capacitor 230 connected through the S/H FET 225 and through the row select FET 60 to the source of the source follower FET 55. The other side of the capacitor 230 is connected to the source bias voltage VSS. The one side of the capacitor 230 is also connected to the gate of an output FET 240. The drain of the output FET 210 is connected through a column select FET 245 to a reset sample output node VOUTR and through a load FET 235 to the drain voltage VDD. The output FET 240, the column select FET 245, and the load FET 235 essentially comprise another output buffer stage of the readout circuit 70. A signal called "reset sample and hold" (SHR) briefly turns on the S/H FET 225 immediately after the reset signal RST has caused the resetting of the potential of the floating diffusion 40, so that the capacitor 230 stores the voltage to which the floating diffusion has been reset.
The readout circuit provides correlated double sampling of the potential of the floating diffusion, in that the charge integrated beneath the photogate 30 each integration period is obtained at the end of each integration period from the difference between the voltages at the output nodes VOUTS and VOUTR of the readout circuit 70. This helps eliminate the effects of fixed pattern noise caused by variations in FETs M55, M60, M45, and M65. In other words, the difference between VOUTS and VOUTR cancels the fixed pattern noise.
The feature of the circuit of FIG. 1 that is useful for eliminating fixed pattern noise due to variations in FET threshold voltage across the substrate 20 is a shorting FET 116 across the sampling capacitors 205 and 230. After the accumulated charge has been measured as the potential difference between the two output nodes VOUTS and VOUTR, a shorting signal VM is temporarily applied to the gate of the shorting FET 116 and the VOUTS-to-VOUTR difference is measured again. This latter difference is a measure of the disparity between the threshold voltages of the output FETs 210 and 240, and may be referred to as the fixed pattern difference. The fixed pattern difference is subtracted from the difference between VOUTS and VOUTR measured at the end of the integration period, to remove fixed pattern noise.
One of the drawbacks of the circuit illustrated in FIG. 1 is that the bit line BL onto which the pixel signals are read has a common mode offset. This common mode offset can make it difficult to reduce the fixed pattern noise once the signal reaches the output buffer stages represented by FETs 210, 215, 220 and FETs 235, 240, 245, respectively, in that the charge injection may be different for different signal levels, and the output buffer stage may have certain nonlinearities. In the prior art circuit of FIG. 1, the buffer stage is limited by the common mode level of the active pixel sensors. In addition, the buffer stage itself, or later stages, may introduce fixed pattern noise of an undesirable proportion of the total signal level.
The present invention is directed to overcoming the foregoing and other disadvantages. More specifically, the present invention is directed to providing a column amplifier for high fixed pattern noise reduction.